-------------------------------------------------------- | | | NanoSim Version G-2012.06 (RHEL64) | | Copyright (c) 2012 Synopsys Inc., All Rights Reserved. | | | -------------------------------------------------------- Built by nsmgr on Fri May 18 18:17:12 PDT 2012 Mon Nov 12 21:29:43 EST 2012 Machine Name: linux-test-64bit Command line options: -n secureFSM_K0_I50.sp -o secureFSM_K0_I50 -c secureFSM_K0_I50.cfg The 64-bit version of the simulator is running. Initializing system messages took 0.010 s LICENSE Information: -- Key: TIMEMILL__NSADDON -- Version: 2012.06 Installing interactive/configuration commands ... Installing commands took 0.000 s Start netlist compilation at Mon Nov 12 21:29:44 2012 Compiling "secureFSM_K0_I50.sp" (SPICE) Compiling "/home/borowcm/libraries/saed90nm.cdl" (SPICE) Compiling "/home/borowcm/libraries/SAED90nm.lib" (SPICE) Compiling "/home/borowcm/libraries/SAED90nm.lib" (SPICE) Compiling "secureFSM_K0_I50_stim.sp" (SPICE) Parsing netlist finished in 0 seconds Default circuit temperature : 25.000 Netlist compilation will be case insensitive. All letters will be converted to lower case. Building instance tree finished in 0 seconds Finish netlist compilation at Mon Nov 12 21:29:44 2012 Netlist compilation took 0.090 s NOTICE:Techfile Voltage (*nanosim tech="voltage") set to 1.2V ... This simulation uses HSPICE models WARNING:NanoSim:0x21104432:MISC MODEL PROBLEM: ** warning** associated with encrypted blocks were suppressed Building node/element arrays took 4.430 s Reading configuration files ... Reading configuration files took 0.000000 s WARNING:NanoSim:0x21108427:Output current waveform sampling resolution (= 1e-15 A) is smaller than the simulation current resolution (= 1e-12 A). # of CMOS elements : 398 # of resistors : 1 # of dc voltage sources : 2 # of independent sources : 3 # of current controlled current sources : 1 # of elements : 405 # of used elements : 404 # of nodes : 197 # of subckt : 342 # of top-level instances : 55 # of capacitors from netlist : 1 # of Ground CAPS from netlist : 1 # of Coupling CAPS from netlist : 0 Circuit partitioning ... Among 1 stages, there are: 0 pwl stages 0 grouped pwl stages 1 analog stages 0 NR stages 0 grouped analog stages 0 rc stages 0 ud stages 0 ADFMI functional model stages 191 nodes in the largest pwl stage 0 nodes in the largest digital stage 1 stages (1 PWL stages) with 150-199 nodes Among 197 nodes, there are: 6 pwl nodes 191 analog (accurate) nodes 0 rc nodes 0 ud nodes 0 cut nodes 0 mem_cut nodes 197 no_clamp nodes 191 nodes in stages 6 voltage source nodes 3 constant nodes 0 NR nodes Among 405 elements, there are: 401 elements in stages 3 pwl elements 20 pwl+ elements 0 synchronous elements 0 SMS elements 378 analog (accurate) elements 0 rc elements 0 ud elements 0 ADFMI functional model elements 0 VERILOGA model elements 0 behavioral model elements 401 mna elements 0 NR elements 0 mos transistors identified as keepers 398 mos transistors need Subthreshold current 0 keepers removed 0 keepers reduced Circuit partitioning took 0.000 s Constructing matrix ... Matrix ordering and construction took 0.000 s After reading configuration file(s), 1 signals are identified to be printed: 1 element branch current signals, including: 1 element branch inst. current signals Statistics of memory used for signal printing: 427288 bytes allocated in total, including: 160000 bytes allocated additionally for node current signals 267288 bytes allocated additionally for element branch current signals Levelizing stages ... Levelizing stages took 0.000 s DC initialization ... WARNING:NanoSim:0x2110e526:Element xnextstate_reg[2].mmp7 outside tech_file range (vg=1.26728, vd=-0.269577, vs=1.2)... at 0ns WARNING:NanoSim:0x2110e5f7:NOTICE: tech_file range is being expanded. WARNING:NanoSim:0x2110e526:Element xnextstate_reg[3].mmp7 outside tech_file range (vg=1.28954, vd=-0.269271, vs=1.2)... at 0ns WARNING:NanoSim:0x2110e5f7:NOTICE: tech_file range is being expanded. WARNING:NanoSim:0x2110e526:Element xu65.mmp4 outside tech_file range (vg=0, vd=0.0613047, vs=1.6)... at 0ns WARNING:NanoSim:0x2110e5f7:NOTICE: tech_file range is being expanded. WARNING:NanoSim:0x2110e526:Element xu43.mmn1 outside tech_file range (vg=0, vd=1.50434, vs=0)... at 0ns WARNING:NanoSim:0x2110e5f7:NOTICE: tech_file range is being expanded. WARNING:NanoSim:0x2110e526:Element xu70.mmp2 outside tech_file range (vg=-0.43751, vd=1.2, vs=1.6)... at 0ns WARNING:NanoSim:0x2110e5f7:NOTICE: tech_file range is being expanded. WARNING:NanoSim:0x2110e526:Element xu70.mmp1 outside tech_file range (vg=-0.436522, vd=1.2, vs=1.6)... at 0ns WARNING:NanoSim:0x2110e5f7:NOTICE: tech_file range is being expanded. WARNING:NanoSim:0x2110e526:Element xu63.mmn5 outside tech_file range (vg=0.24277, vd=1.6, vs=0)... at 0ns WARNING:NanoSim:0x2110e5f7:NOTICE: tech_file range is being expanded. WARNING:NanoSim:0x2110e526:Element xu62.mmp1 outside tech_file range (vg=-0.436522, vd=1.2, vs=1.6)... at 0ns WARNING:NanoSim:0x2110e5f7:NOTICE: tech_file range is being expanded. WARNING:NanoSim:0x2110e526:Element xu38.mmp1 outside tech_file range (vg=-0.199939, vd=1.2, vs=1.6)... at 0ns WARNING:NanoSim:0x2110e5f7:NOTICE: tech_file range is being expanded. WARNING:NanoSim:0x2110e526:Element xu38.mmp2 outside tech_file range (vg=-0.43751, vd=1.2, vs=1.6)... at 0ns WARNING:NanoSim:0x20102001:Previous message has been printed 10 times, It will not be printed again! To change the limit for every message type, use: "set_mesg_opt limit_per_mesg=" WARNING:NanoSim:0x2110e5f7:NOTICE: tech_file range is being expanded. WARNING:NanoSim:0x20102001:Previous message has been printed 10 times, It will not be printed again! To change the limit for every message type, use: "set_mesg_opt limit_per_mesg=" Finishing initialization (level 0 -- 0) 0 dynamic stages assigned in DC Initialization Number of residual dc events scheduled : 0 Number of ic nodes scheduled : 0 DC initialization took 0.030 s Simulation begins in pwl mode ... WARNING:NanoSim:0x2110f524:Positive bulk-source bias: element xu37.mmn4, vbs=0.400086... at 25.03ns WARNING:NanoSim:0x2110f524:Positive bulk-source bias: element xu37.mmn3, vbs=0.400086... at 25.03ns WARNING:NanoSim:0x2110f526:Element xnextstate_reg[1].mmp1 outside tech_file range (vg=1.14151, vd=-0.373008, vs=1.19983)... at 25.09ns WARNING:NanoSim:0x2110f5f7:NOTICE: tech_file range is being expanded. WARNING:NanoSim:0x2110f526:Element xnextstate_reg[1].mmp3 outside tech_file range (vg=1.12354, vd=-0.373008, vs=1.19512)... at 25.09ns WARNING:NanoSim:0x2110f5f7:NOTICE: tech_file range is being expanded. WARNING:NanoSim:0x2110f526:Element xnextstate_reg[1].mmn3 outside tech_file range (vg=-0.0107747, vd=1.19512, vs=-0.373008)... at 25.09ns WARNING:NanoSim:0x2110f5f7:NOTICE: tech_file range is being expanded. WARNING:NanoSim:0x2110f526:Element xnextstate_reg[2].mmp1 outside tech_file range (vg=1.14876, vd=-0.407536, vs=1.19981)... at 25.09ns WARNING:NanoSim:0x2110f5f7:NOTICE: tech_file range is being expanded. WARNING:NanoSim:0x2110f524:Positive bulk-source bias: element xnextstate_reg[2].mmn1, vbs=0.407536... at 25.09ns WARNING:NanoSim:0x2110f526:Element xnextstate_reg[2].mmp3 outside tech_file range (vg=1.12968, vd=-0.407536, vs=1.19556)... at 25.09ns WARNING:NanoSim:0x2110f5f7:NOTICE: tech_file range is being expanded. WARNING:NanoSim:0x2110f524:Positive bulk-source bias: element xnextstate_reg[2].mmn3, vbs=0.407536... at 25.09ns WARNING:NanoSim:0x2110f526:Element xnextstate_reg[2].mmn3 outside tech_file range (vg=-0.0100889, vd=1.19556, vs=-0.407536)... at 25.09ns WARNING:NanoSim:0x2110f5f7:NOTICE: tech_file range is being expanded. WARNING:NanoSim:0x2110f524:Positive bulk-source bias: element xu50.mmn2, vbs=0.418276... at 29.99ns WARNING:NanoSim:0x2110f524:Positive bulk-source bias: element xu50.mmn1, vbs=0.418276... at 29.99ns WARNING:NanoSim:0x2110f526:Element xu50.mmn1 outside tech_file range (vg=-0.0135611, vd=1.21018, vs=-0.418276)... at 29.99ns WARNING:NanoSim:0x2110f5f7:NOTICE: tech_file range is being expanded. WARNING:NanoSim:0x2110f524:Positive bulk-source bias: element xu53.mmn2, vbs=0.412504... at 29.99ns WARNING:NanoSim:0x2110f524:Positive bulk-source bias: element xu53.mmn1, vbs=0.412504... at 29.99ns WARNING:NanoSim:0x2110f526:Element xu53.mmn1 outside tech_file range (vg=-0.0116529, vd=1.21029, vs=-0.412504)... at 29.99ns WARNING:NanoSim:0x2110f5f7:NOTICE: tech_file range is being expanded. Simulation ends at 540.000 ns Simulation took 1.070 s Current information calculated over the intervals: 0.00000e+00 - 5.40010e+02 ns Simulation time resolution : 1.000e-02 ns Print time resolution : 1.000e-02 ns Number of PWL matrix solutions : 2613 Number of PWL MOS model lookups : 1005805 Number of time steps : 2529 Number of iterations : 0 Number of rejected time steps : 173 Global simulation parameters used: SPD 0.06V ASPD 0.024V SIM_DESV 0.06V SIM_AESV 0.024V VDS_MIN 9.34266e-11V AVDS_MIN 9.34266e-11V SSC (steady state current) 1e-07uA SUBI (subthreshold current) 1e-06uA DC CURRENT 1e-06uA 6.0 real 6.1 user 0.1 sys Signal data is saved in secureFSM_K0_I50.out No errors reported in the .err file (secureFSM_K0_I50.err)